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The role involves leading the physical design of ASICs, overseeing all phases from RTL to GDSII, and enhancing design methodologies.

Lead ASIC and platform development, manage cross-functional teams, oversee project timelines, budgets, and vendor relationships to ensure successful program delivery.

The Staff DFT Engineer will define and implement DFT strategies and methodologies, work with cross-functional teams, and support device bring-up for high-volume manufacturing.

Lead and scale a design verification team for PHY and controller products. Define verification strategy and methodology (UVM, AMS, formal), drive verification planning and execution across link layer, PCS, PMA, and FEC, integrate analog models into digital flows, manage tapeout verification milestones, improve verification infrastructure and CI/CD, ensure standards compliance, and oversee vendor VIPs and firmware co-simulation for tapeout readiness.

The Senior Staff Physical Verification Engineer leads all physical verification activities including DRC, LVS, and DFM for advanced chip designs, ensuring compliance across multiple foundries and technologies.