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Lead architecture and RTL implementation of high-speed SerDes digital IP (224G/448G PAM4), including DSP equalization, CDR, FEC, PHY control, RTL quality, AMS integration, tapeout coordination, standards work, firmware interfaces, and post-silicon debug.

Lead end-to-end execution of IP, ASIC, and chiplet platform programs from architecture through production readiness. Build and manage integrated schedules, drive critical-path closure, coordinate cross-functional engineering teams, manage vendors and customers, mitigate risks, control budget and resources, run technical reviews, and report program health to executives while improving program processes and tooling.

As a Principal Physical Design Engineer, you will lead ASIC development from RTL to GDSII, oversee design flow optimization, and ensure the delivery of high-performance products.

The role involves leading the physical design of ASICs, overseeing all phases from RTL to GDSII, and enhancing design methodologies.

Lead and scale a design verification team for PHY and controller products. Define verification strategy and methodology (UVM, AMS, formal), drive verification planning and execution across link layer, PCS, PMA, and FEC, integrate analog models into digital flows, manage tapeout verification milestones, improve verification infrastructure and CI/CD, ensure standards compliance, and oversee vendor VIPs and firmware co-simulation for tapeout readiness.