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As a Staff Digital Verification Engineer, develop verification plans, maintain test environments, and ensure compliance with Ethernet standards while leading junior engineers.

This role involves managing digital design flow infrastructure, including automation, quality control, and utilizing AI tooling for review processes. A mentorship path to digital design ownership is included.

Lead the verification of Serdes systems, develop UVM/SV testbenches and test cases, and mentor junior engineers while ensuring design quality and integration.

Lead the frontend digital design of D2D PHY for chiplet systems, optimizing performance and collaborating across teams while mentoring junior designers.

The Principal Digital Verification Engineer will lead technical verification of chiplet products, develop UVM-based test environments, execute verification plans, and mentor junior engineers.

As a Digital Design Engineer at Eliyan, you will design and develop Ethernet PCS/PMA IPs, optimize digital designs, and collaborate on high-performance products.

The Senior Staff Physical Verification Engineer leads all physical verification activities including DRC, LVS, and DFM for advanced chip designs, ensuring compliance across multiple foundries and technologies.

Lead architecture and RTL implementation of high-speed SerDes digital IP (224G/448G PAM4), including DSP equalization, CDR, FEC, PHY control, RTL quality, AMS integration, tapeout coordination, standards work, firmware interfaces, and post-silicon debug.

As a Signal and Power Integrity Engineer, you'll develop packaging solutions for chiplet interconnects, optimizing performance through simulation, measurement, and collaboration with cross-functional teams.

Lead STA signoff processes for complex ASIC designs, defining methodologies and collaborating with design teams to ensure timing closure and optimal performance.