As a Senior Formal Verification Engineer, you will verify ASICs using formal methods, collaborate multi-functionally, lead methodology enhancements, and mentor junior engineers while ensuring compliance and correctness.

You will verify ASIC design implementation, develop verification infrastructure, optimize verification flows, and collaborate with teams on advanced methodologies.

As a Senior ASIC Design Engineer, you'll implement high-performance RTL, analyze architectural trade-offs, and collaborate across teams to deliver cutting-edge designs.