Lead architecture and execution for petabyte-scale ingestion pipelines. Define platform technical vision, set cross-team engineering standards, drive multi-team programs to improve scale, performance, security, and reliability, and mentor senior engineers.

Lead architecture, design, layout, measurement and productization of ultra-deep-submicron CMOS mixed-signal ICs for high-speed optical transceivers. Mentor engineers, manage a large block on complex chips, collaborate with package/hardware teams for signal and power integrity, and drive designs from concept to production.

Lead full-chip physical design activities including floorplanning, hierarchical implementation (partition, pin assignment, clock and bump planning), RTL-to-GDSII flow, timing closure, power grid planning, power integrity and physical verification. Collaborate with RTL, DFT, package, foundry, IP vendors and EDA teams to optimize performance, power, and die size, and improve tool flows and methodologies. Apply low-power UPF flows and leverage Python and AI tools to boost productivity.