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Contribute to physical implementation of AI accelerator ASICs from floorplanning and macro placement through tapeout. Responsibilities include clock tree synthesis, place and route, timing, power, signal integrity, IR/EM, DRC, LVS, congestion, ECOs, metal fill, and signoff closure. The role also supports implementation methodology, advanced-node tapeouts, AI-enabled QoR analysis, and collaboration with RTL, synthesis, DFT, package, and backend teams.

Lead architecture and performance exploration for next-generation AI inference accelerators. Build analytical models and simulation frameworks, define subsystem interfaces and roadmaps, and drive hardware/software co-design with compiler, runtime, ML, and silicon teams to optimize latency, throughput, memory, interconnects, power, and cost for evolving LLMs and transformer-based workloads.

Lead synthesis, timing convergence, and implementation readiness for AI accelerators. Own synthesis flows, SDC constraints, timing closure, physical-aware optimization, vendor coordination, and apply automation/AI to improve QoR and timing debug across multi-million-gate designs.

Lead power architecture, modeling, optimization, and verification for AI accelerators. Develop lifecycle power models, drive low-power techniques (clock/power gating, voltage islands), own UPF/CPF flows and power-aware verification, partner with cross-functional teams on power integrity and silicon validation, and apply AI tools to improve power analysis and anomaly detection.