Top Tech Jobs & Startup Jobs in Vancouver

Owns the GitHub-based build and release environment, including CI/CD pipelines, runners, testing, packaging, and artifact publishing. Improves build speed, reliability, security, and release repeatability while managing cloud compute resources. Troubleshoots complex build, test, and infrastructure failures, monitors system health, and documents architecture and procedures. Collaborates with engineers to improve tooling and communicates build status, incidents, and changes clearly.

Create technical content explaining Efficient Computer’s processor architecture, compiler, benchmarks, applications, and energy-efficiency results. Responsibilities include writing blogs, application notes, white papers, newsletters, web pages, scripts, presentations, and sales materials; hands-on evaluation hardware bring-up, software compilation, measurement, data analysis, demos, and technical reviews; and supporting webinars, conferences, and content optimization. The role requires an engineering background, strong technical writing, C or C++, development hardware experience, and Python or similar data-analysis skills.

Lead end-to-end functional verification for complex ASIC and SoC designs from specification through tapeout. Define verification strategy, architect UVM testbenches, drive constrained-random testing and coverage closure, manage regressions and bug lifecycles, debug complex failures, support CDC/RDC and gate-level simulation, coordinate emulation handoff, and lead verification sign-off. Mentor and grow the verification team while collaborating with compiler, RTL, DFT, physical design, and post-silicon teams.

Develop and maintain UVM/SystemVerilog verification environments for ASIC and SoC blocks and subsystems. Create verification plans, assertions, functional coverage models, constrained-random tests, and regression automation. Debug simulation failures, drive coverage closure, support gate-level simulation and sign-off, and collaborate with RTL designers and architects. The role requires 4+ years of ASIC/SoC design verification experience, including multiple tapeouts, plus Python automation skills.

Manage semiconductor supply chain and operations during the transition from prototype to production. Responsibilities include sourcing and procuring third-party semiconductor IP, negotiating commercial terms, evaluating vendors with engineering teams, managing logistics and international trade operations, supporting foundry and OSAT activities, analyzing costs, maintaining supply chain procedures and trackers, and escalating risks. The role also supports planning, inventory, supplier relationships, and process development in a fast-moving startup environment.

Design, integrate, and sign off synthesizable RTL for ultra-low-power SoC blocks, including compute fabric interconnects, memory interfaces, peripherals, low-power logic, and power-management systems. Own front-end quality through lint, CDC/RDC, LEC, synthesis, timing, and power analysis. Support verification, gate-level debugging, physical-design closure, tapeout, and silicon bring-up while collaborating with architecture, DV, physical design, and firmware teams.

Own verification for complex SoC blocks and subsystems from specification review through coverage sign-off. Build and extend UVM/SystemVerilog environments, develop assertions and coverage models, debug simulations, drive coverage closure, report verification risks, and document environments. The role requires extensive ASIC/SoC verification experience, strong scripting skills, independent execution, and collaboration with RTL designers and architects. Preferred experience includes C/C++, formal verification, AI-assisted verification, computer architecture, ML accelerators, and power-aware verification.

Own the Linux user-mode runtime, driver, and HAL interfaces for a Fabric accelerator. Responsibilities include runtime library design, compiler and kernel-driver integration, memory and resource management, ML framework backends, pre-silicon bring-up using simulation, emulation, QEMU, and FPGAs, and comprehensive runtime testing. Collaborate across compiler, architecture, verification, and kernel teams to support first-silicon deployment.

Own development of a Linux kernel-mode driver for a custom Fabric accelerator, including memory management, SMMU/IOMMU integration, MMIO, interrupts, power management, firmware, and user-space interfaces. Lead pre-silicon enablement using QEMU, simulation, emulation, and FPGA platforms; manage Linux boot and first-silicon bring-up. Debug complex hardware and kernel issues, establish automated testing, and collaborate with architecture, verification, compiler, and hardware teams.

Lead microarchitecture definition and synthesis-ready RTL implementation for processor and accelerator SoCs. Own dataflow execution fabrics, memory subsystems, on-chip networks, low-power logic, peripheral integration, and hardware/software execution models. Drive PPA optimization, verification collaboration, design documentation, mentoring, synthesis and timing closure, DFT support, tape-out, and silicon bring-up for highly energy-efficient edge-computing hardware.