Lead architecture and RTL implementation of high-speed SerDes digital IP (224G/448G PAM4), including DSP equalization, CDR, FEC, PHY control, RTL quality, AMS integration, tapeout coordination, standards work, firmware interfaces, and post-silicon debug.

Top Skills: Systemverilog,Rtl,Lint,Cdc,Rdc,Synthesis,Dft,Finfet,Gaa,5Nm,3Nm,Pam4,Rs-Fec Kp4,Rs-Fec Kp8,Ffe,Dfe,Mlse,Ctle,Cdr,Oif Cei,Ieee 802.3,Ucie,Dac,Adc,Ams Co-Simulation,Dpi

Eliyan Corporation

Director of Design Verification

24 Days AgoSaved

In-Office or Remote

7 Locations

Expert/Leader

Information Technology • Manufacturing

Lead and scale a verification organization for PHY and controller products, owning end-to-end verification strategy across link layer, PCS, PMA, FEC, and AMS flows. Build teams, drive UVM/RNM/AMS methodologies, manage tapeout verification milestones, vendor VIP integration, CI/CD and coverage-driven signoff, and ensure standards compliance (IEEE 802.3, UCIe).

Top Skills: Ai/Ml-Assisted VerificationCdrCi/CdConstrained-Random VerificationCoverage AnalyticsCoverage-Driven VerificationDftDllDpiDram ControllersEthernet (100G/200G/400G/800G)Formal VerificationGate-Level Simulation (Gls)HbmIeee 802.3Kp4Kr4PllReal-Number Modeling (Rnm)Rs-FecSerdesSvamsSystemverilogSystemverilog Assertions (Sva)UcieUvmVerilog-Ams

Eliyan Corporation

Package & SI/PI - Signal and Power Integrity Engineer

Reposted 25 Days AgoSaved

In-Office or Remote

7 Locations

Senior level

Information Technology • Manufacturing

As a Signal and Power Integrity Engineer, you'll develop packaging solutions for chiplet interconnects, optimizing performance through simulation, measurement, and collaboration with cross-functional teams.

Top Skills: AdsAllegroHfssHspicePowerdcPowersiQ3DSiwaveSpectre

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