Lead customer-facing technical engagements for Scorpio switch platforms, drive post-silicon validation and system integration, debug complex protocol and SI/firmware issues, mentor engineers, produce technical collateral, and influence product roadmap and feature validation across PCIe Gen6/Gen7, UALink, and related interconnects.

Lead RTL design and implementation for complex interconnect blocks from microarchitecture through synthesis sign-off. Collaborate with architecture, verification, DFT, and physical design teams to achieve timing closure and silicon-quality deliverables. Mentor junior engineers, drive design methodology, debug pre- and post-silicon issues, and support tapeout schedules for PCIe/CXL/Ethernet and related high-speed interfaces.