Top Tech Jobs & Startup Jobs in Vancouver

As a Senior Engineer, develop low-level firmware for Ethernet components, drive silicon bring-up, and optimize networking hardware. Collaborate closely with silicon architects and debug hardware-software interactions.

As an AI Processor IP Product Engineer, you'll facilitate customer integration of AI processors into SoCs, ensuring performance and market readiness. Responsibilities include technical support and debugging complex systems.

Lead and scale accounting operations (AP, AR, payroll accounting, fixed assets, accruals, reconciliations, and close). Improve close cycle, strengthen internal controls, drive ERP/process automation, build a high-performing global team, and manage auditors, consultants, and outsourced partners to support rapid growth and public-company readiness.

Senior-level program manager and chief of staff supporting the CVP of Operations. Own and drive high-priority cross-functional programs from kickoff through execution, establish operating cadences, align teams on priorities, prepare leadership materials, integrate sales & operations, headcount and infrastructure planning, surface risks, and remove execution blockers to ensure organizational KPIs and milestones are met.

Define and own chiplet-based compute platform architectures for high-performance RISC-V CPUs in SiP solutions. Lead design of PCIe, die-to-die connectivity, coherent fabrics, system management, and confidential computing subsystems. Collaborate with architecture, hardware, software, and external IP partners to deliver production-ready chiplet architectures and drive cross-functional execution.

Design and deliver die-to-die chiplet PHY IP in advanced FinFET nodes: develop PLLs and AMS blocks, lead design verification and layout interactions, support tape-out and silicon bring-up, and collaborate across architecture, digital, verification, layout, and software teams to achieve production-quality silicon.

Define architecture and micro-architecture specs for memory and I/O chiplets, evaluate next-generation memory technologies, develop performance and power modeling infrastructure, and collaborate with SoC, verification, physical design, packaging, systems teams and external partners to enable high-throughput, low-latency memory architectures.

Lead hardware-software co-design to enable AI/HPC and agentic AI stacks on RISC-V CPUs. Integrate and optimize low-level kernel infrastructure, runtimes, distributed execution, memory systems, and developer tools, collaborating with architects, compiler engineers, and kernel developers to meet performance targets.