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Ethernovia

Senior ASIC Design Verification Engineer

Reposted 17 Days AgoSaved
Remote
Canada
Senior level
Senior level
Industrial • Manufacturing
The Senior ASIC Design Verification Engineer is responsible for digital SoC verification, collaborating with architects and engineers to validate automotive communication semiconductors and systems.
Top Skills: Verilog,System Verilog,Uvm,Python,Tcl,C/C++
Ethernovia Logo
Ethernovia

Senior ASIC (Front End) Design Engineer

Reposted 17 Days AgoSaved
Remote
Canada
Senior level
Senior level
Industrial • Manufacturing
As a Senior ASIC Design Engineer, you will handle digital SoC design, collaborating to deliver high-performance automotive communication semiconductors and systems.
Top Skills: Asic RtlC/C++EthernetPciePerlSystem VerilogTclTcp/IpVerilog
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