Teams at Positron AI

Own end-to-end FPGA and ASIC development from microarchitecture and SystemVerilog RTL through implementation, timing closure, simulation, and lab validation. Design networking and digital logic functions, build FPGA prototypes, bring up systems combining FPGA, firmware, and software, and optimize cost, size, power, performance, and features for AI inference platforms.

Lead power architecture, modeling, optimization, and verification for AI accelerators. Develop lifecycle power models, drive low-power techniques (clock/power gating, voltage islands), own UPF/CPF flows and power-aware verification, partner with cross-functional teams on power integrity and silicon validation, and apply AI tools to improve power analysis and anomaly detection.

Own synthesis, timing closure, constraint development, and implementation readiness for ASIC accelerator partitions. Execute Cadence Genus or Synopsys Design Compiler flows, develop SDC and MMMC environments, optimize timing, area, power, and congestion, and collaborate with RTL, verification, DFT, physical design, and backend teams. Improve synthesis methodology, analyze QoR and timing bottlenecks, support vendor partners, and apply AI tools to engineering automation and report analysis.