Teams at Cisco

Design, simulate, lay out, measure, and productize high-speed analog and mixed-signal CMOS ICs for optical communications. Lead complex chip blocks, mentor engineers, track deliverables, conduct peer reviews, and establish design methodology through production. Collaborate with RF, digital/DSP, packaging, hardware, and module teams to meet signal and power integrity requirements. Perform laboratory validation, characterization, and advanced layout and manufacturability analysis.

Develops full-chip ASIC physical design flows from RTL to GDSII, including floorplanning, power grid planning, placement, routing, timing analysis, power integrity, physical verification, and equivalence checks. The role optimizes performance, power, and die size for advanced process nodes, enhances EDA methodologies, collaborates with RTL, DFT, foundry, IP, and vendor teams, and supports signoff and post-silicon validation.

Lead architecture and execution for petabyte-scale ingestion pipelines. Define platform technical vision, set cross-team engineering standards, drive multi-team programs to improve scale, performance, security, and reliability, and mentor senior engineers.