Jobs at Cisco

Design, simulate, lay out, measure, and productize high-speed analog and mixed-signal CMOS ICs for optical communications. Lead complex chip blocks, mentor engineers, track deliverables, conduct peer reviews, and establish design methodology through production. Collaborate with RF, digital/DSP, packaging, hardware, and module teams to meet signal and power integrity requirements. Perform laboratory validation, characterization, and advanced layout and manufacturability analysis.

Develops full-chip ASIC physical design flows from RTL to GDSII, including floorplanning, power grid planning, placement, routing, timing analysis, power integrity, physical verification, and equivalence checks. The role optimizes performance, power, and die size for advanced process nodes, enhances EDA methodologies, collaborates with RTL, DFT, foundry, IP, and vendor teams, and supports signoff and post-silicon validation.

Lead architecture and execution for petabyte-scale ingestion pipelines. Define platform technical vision, set cross-team engineering standards, drive multi-team programs to improve scale, performance, security, and reliability, and mentor senior engineers.

Lead full-chip physical design activities including floorplanning, hierarchical implementation (partition, pin assignment, clock and bump planning), RTL-to-GDSII flow, timing closure, power grid planning, power integrity and physical verification. Collaborate with RTL, DFT, package, foundry, IP vendors and EDA teams to optimize performance, power, and die size, and improve tool flows and methodologies. Apply low-power UPF flows and leverage Python and AI tools to boost productivity.

Drive the full sales cycle for public and private sector accounts, collaborating with Cisco partners, solution engineers, and specialists. Responsibilities include meeting quota, developing territory plans, managing at least 50 accounts, building pipeline, forecasting accurately, articulating Cisco’s value proposition, and maintaining customer and partner relationships. The role is hybrid, Canada-based, and involves occasional travel for key engagements.

Lead architecture, design, layout, measurement and productization of ultra-deep-submicron CMOS mixed-signal ICs for high-speed optical transceivers. Mentor engineers, manage a large block on complex chips, collaborate with package/hardware teams for signal and power integrity, and drive designs from concept to production.