Lead and manage physical design teams, execute design strategy, optimize ASIC design flows, collaborate with cross-functional teams, and ensure successful tapeout.
Eliyan corporation develops chiplets to solve compelling Bandwidth and Scale Out solutions for next generation AI/Data center applications. We design the lowest power and area products to meet high-speed interfaces.
Come and join us and take part in Eliyan’s groundbreaking solutions, you will be interfacing with the demanding customers to provide the solutions they need. We offer a fun work environment with excellent benefits. ONSITE M-F
Key Responsbilities
- Lead and manage a team of physical design engineers, providing technical direction, mentorship, and performance feedback.
- Define and execute the physical design strategy for multiple projects, ensuring alignment with company goals and timelines.
- Develop, optimize, and maintain ASIC design flows for synthesis, PnR, EM/IR analysis, STA, and PV.
- Drive continuous improvements in flow efficiency, automation, and quality metrics to meet power, performance, and area (PPA) targets.
- Own the complete ASIC physical design process, from RTL handoff to GDSII delivery.
- Collaborate with front-end design teams on RTL readiness and design-for-test (DFT) requirements.
- Oversee logic synthesis, ensuring adherence to timing, power, and area constraints.
- Drive floor planning, placement, clock tree synthesis (CTS), routing, and physical optimization in PnR.
- Manage EM/IR analysis, timing closure through STA, and physical verification, including DRC, LVS, and metal fill.
- Ensure successful tapeout with full sign-off criteria met, including reliability and manufacturability requirements.
- Work closely with cross-functional teams, including front-end design, DFT, package engineering, and manufacturing.
- Present project updates and status reports to executive leadership.
Minimum Qualifications
- Expertise in multiple areas of physical design, timing, and signoff
- Strong scripting and automation skills
- Management of small team experience
- Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field
Ideal Qualifications
- 12+ years of experience in ASIC physical design, with a proven track record of leading teams through successful tapeouts
- Deep expertise in the following areas: o RTL-to-GDSII flows o Synthesis, PnR, STA, EM/IR, and PV o Physical design for advanced process node (5nm and below) across two or more foundries
- Strong knowledge of EDA tools (Synopsys or Cadence) and scripting (Python, Perl).
- Exceptional leadership, project management, and problem-solving skills.
Top Skills
Asic Design
Cadence
Perl
Python
Rtl-To-Gdsii Flows
Synopsys
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